For the past several decades, the scaling of features in integrated circuits has enabled increased densities of functional units on a semiconductor chip. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, leading to the fabrication of products with increased capacity.
In the manufacture of field effect transistors (FETs) for integrated circuit devices, semiconducting crystalline materials other than silicon may be advantageous. An example of one such material is Ge, which offers a number of potentially advantageous features relative to silicon, such as, but not limited to, high charge carrier (hole) mobility, band gap offset, a different lattice constant, and the ability to alloy with silicon to form semiconducting binary alloys of SiGe.
One problem with the use of Ge in modern transistor designs is that the extremely fine features (e.g., 22 nm and below) that are now achieved for silicon FETs aggressively scaled over the years are now difficult to achieve in Ge, often making potential material-based performance gains a wash when implemented in less-aggressively scaled forms. The difficulty in scaling is related to the material properties of Ge, and more particularly difficulty in etching SiGe, which is often employed as an intermediate layer between a Ge active layer (e.g., transistor channel layer) and an underlying silicon substrate material, with sufficient selectively over Ge so as to remove the SiGe without eroding a finely printed Ge active layer feature.
Material stack architectures and etching techniques which enable high SiGe:Ge etch selectively are therefore advantageous.